module alu #(
    parameter N = 32
)
(
    input       [2:0]       alu_control,    //000:ADD 001:Subtract 101:SLT 011:OR 010:AND
    input       [N-1:0]     srcA,
    input       [N-1:0]     srcB,
    output  reg [N-1:0]     alu_result,
    output                  zero
);

wire [N-1:0] add_src1;
wire [N-1:0] add_src2;
wire [N-1:0] sum;
wire         overflow;

assign add_src1 = alu_control[0] ? ~srcB : srcB; //加法使用原码 减法使用补码
assign add_src2 = srcA;
assign sum = add_src1 + add_src2 + {31'b0,alu_control[0]};
assign overflow = ~alu_control[1] & (sum[N-1] ^ srcA[N-1]) & ~(alu_control[0] ^ srcA[N-1] ^ srcB[N-1]); //溢出指示 例如（-3）-7 = 2
assign zero = (alu_result == 0);

always @(*) begin
    case(alu_control)
    3'b000 : alu_result = sum;                  //ADD
    3'b001 : alu_result = sum;                  //Subtract
    3'b010 : alu_result = srcA & srcB;          //AND
    3'b011 : alu_result = srcA | srcB;          //OR
    3'b100 : alu_result = srcA ^ srcB;          //XOR
    3'b101 : alu_result = {31'b0,overflow ^ sum[N-1]};  //SLT x[rd] = signed(x[rs1] < x[rs2])
    default: alu_result = 0;
    endcase
end
    
endmodule
